In standard logic complementary metal oxide semiconductor (CMOS) process, transistors fabricated have gate oxides that enable non-volatile memory (NVM) to retain charge on a floating gate. The thinnest silicon dioxide gate oxide that can be used to retain charge on the floating gate is around 50 Angstrom (A). A 50 A gate oxide is typically used for a 2.5V device in the standard logic CMOS process. Currently, the NVM charge retention time is 10 years. However, when the 50 A gate oxide is scaled below 50 A the charge retention time is reduced below 10 years due to direct tunneling.
Standard logic CMOS processes typically have two or more gate oxide thicknesses. One oxide thickness is used for core logic devices and a second thicker oxide is used for Input/Output (I/O) of the chip. I/O voltage typically needs to be large since it is driving very long chip to chip interconnects. Typically, an I/O device is operable at 2.5V or higher. However, as technology continues to scale to smaller devices and lower voltages, the I/O devices also need to be scaled to smaller dimensions and smaller voltages. When the I/O devices are scaled down to 1.8V (the next step below 2.5V), floating gate NVM having standard 10 year retention is no longer possible.
Further, the charge retention time for devices that support 1.8V is less than 1 year. Hence to increase the charge retention time, ideally another gate oxide can be added by thermal oxidation to create thicker gate oxide. However, growing another gate oxide by thermal oxidation adds a lot of heat to the process. Deep sub-micron processes are sensitive to heat and the additional heat causes dopants in the semiconductor material to diffuse. In many processes the additional diffusion affect the performance of the other devices, which is not acceptable. There is a need for a method to solve the above mentioned problems.